Show HN: A Project Oberon System Version Running On RISC-V Instead Of RISC-5

A developer has shared a version of the Project Oberon operating system running on RISC-V hardware, replacing the original RISC-5 platform. This port demonstrates the system’s adaptability and offers potential for broader hardware experimentation, crucial for educational and research purposes.

The port was shared via a Show HN post, with the developer detailing the process of adapting the Oberon system—originally designed for the RISC-5 architecture—to the open-source and increasingly popular RISC-V architecture. The work involved modifying low-level hardware interfaces and ensuring compatibility with RISC-V’s instruction set, which differs significantly from RISC-5.

According to the developer, the port is functional and capable of running core Oberon features, including its minimalist GUI and file system. The effort was partly motivated by RISC-V’s open design and growing adoption in academia and industry, aiming to demonstrate Oberon’s portability and to explore its potential on modern hardware platforms.

Implications for Operating System Education and Research

This development highlights the flexibility of the Oberon system and its suitability as a teaching tool for operating system concepts, especially on open hardware like RISC-V. It showcases how minimalist OS designs can be adapted across architectures, encouraging experimentation and innovation in OS research.

Moreover, the move to RISC-V, an open instruction set architecture, aligns with broader trends toward open hardware, potentially enabling wider access to Oberon for educational institutions and hobbyists interested in OS development and hardware-software integration.

Background on Project Oberon and RISC-V Adoption

Project Oberon, developed by Niklaus Wirth and colleagues at ETH Zurich, is a minimalist operating system designed for simplicity and efficiency. Originally built for the RISC-5 architecture, it has served as a teaching and research platform for decades.

RISC-V, an open-source instruction set architecture, has gained popularity over recent years due to its flexibility, modularity, and absence of licensing restrictions. Its adoption spans academia, industry, and hobbyist communities, prompting efforts to port existing systems and OSes to RISC-V hardware.

This port of Oberon to RISC-V builds on growing interest in open hardware and the desire to demonstrate the system’s portability beyond its original platform.

“This port shows that Oberon can run on modern, open hardware, and could serve as a basis for further OS experimentation on RISC-V.”

— the developer posting on Show HN

Extent of System Functionality and Compatibility on RISC-V

It is not yet clear how fully functional the RISC-V version of Oberon is, particularly regarding peripheral support, performance benchmarks, and stability under extended use. The port appears to run core features, but comprehensive testing results are not yet available.

Additionally, details about the specific hardware used for testing and whether the port supports all features of the original system remain undisclosed.

Next Steps for Testing and Community Adoption

The developer plans to continue testing the RISC-V port, aiming to improve hardware support and stability. Community feedback and contributions could facilitate further development, including porting additional Oberon features and expanding hardware compatibility.

Potential future milestones include benchmarking performance, integrating with various RISC-V boards, and releasing detailed documentation to encourage broader experimentation.

Key Questions

What is Project Oberon?

Project Oberon is a minimalist operating system and programming environment developed at ETH Zurich, designed for simplicity and efficiency, primarily for educational and research purposes.

Why port Oberon to RISC-V?

Porting Oberon to RISC-V demonstrates its portability and supports the trend toward open hardware, enabling wider access for learning, experimentation, and OS research on modern architectures.

Does the RISC-V version support all features of the original Oberon system?

It is currently unclear how complete the port is regarding peripheral support and stability; initial reports indicate core features run, but comprehensive testing is ongoing.

Who developed this port?

The port was shared by an individual developer via a Show HN post, with no official affiliation announced.

What are the implications for OS development on open hardware?

This port showcases how legacy systems can be adapted to new hardware platforms, encouraging experimentation and innovation in open hardware and OS research.

Source: hn